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Iterative schedule optimization for voltage scalable distributed embedded systems

Published:01 February 2004Publication History
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Abstract

We present an iterative schedule optimization for multirate system specifications, mapped onto heterogeneous distributed architectures containing dynamic voltage scalable processing elements (DVS-PEs). To achieve a high degree of energy reduction, we formulate a generalized DVS problem, taking into account the power variations among the executing tasks. An efficient heuristic is presented that identifies optimized supply voltages by not only "simply" exploiting slack time, but under the additional consideration of the power profiles. Thereby, this algorithm minimizes the energy dissipation of heterogeneous architectures, including power-managed processing elements, effectively. Further, we address the simultaneous schedule optimization toward timing behavior and DVS utilization by integrating the proposed DVS heuristic into a genetic list scheduling approach. We investigate and analyze the possible energy reduction at both steps of the co-synthesis (voltage scaling and scheduling), including the power variations effects. Extensive experiments indicate that the presented work produces solutions with high quality.

References

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            cover image ACM Transactions on Embedded Computing Systems
            ACM Transactions on Embedded Computing Systems  Volume 3, Issue 1
            February 2004
            232 pages
            ISSN:1539-9087
            EISSN:1558-3465
            DOI:10.1145/972627
            Issue’s Table of Contents

            Copyright © 2004 ACM

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            Publication History

            • Published: 1 February 2004
            Published in tecs Volume 3, Issue 1

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