Abstract
Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multicore Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multihop links with high latency and power consumption. This limitation can be addressed by drawing inspiration from the evolution of natural complex networks, which offer great performance-cost trade-offs. Analogous with many natural complex systems, future multicore chips are expected to be hierarchical and heterogeneous in nature as well. In this article we undertake a detailed performance evaluation for hierarchical small-world NoC architectures where the long-range communications links are established through the millimeter-wave wireless communication channels. Through architecture-space exploration in conjunction with novel power-efficient on-chip wireless link design, we demonstrate that it is possible to improve performance of conventional NoC architectures significantly without incurring high area overhead.
- AGILENT 2012. Advanced Design System (ADS). http://www.home.agilent.comGoogle Scholar
- Albert, R. and Barabasi, A.-L. 2002. Statistical mechanics of complex networks. Rev. Modern Phys. 74, 47--97.Google ScholarCross Ref
- Branch, J., Guo, X., Gao, L., Sugavanam, A., Lin, J.-J., and O, K. K. 2005. Wireless communication in a flip-chip package using integrated antennas on silicon substrates. IEEE Electron. Dev. Lett. 26, 2, 115--117.Google ScholarCross Ref
- Buchanan, M. 2003. Nexus: Small Worlds and the Groundbreaking Theory of Networks. W.W. Norton & Company, Inc. Google ScholarDigital Library
- Chang, M. F., Cong, J., Kaplan, A., Naik, M., Reinman, G., Socher, E., and Tam, S.-W. 2008. CMP network-on-chip overlaid with multi-band RF-interconnect. In Proceedings of the IEEE International Symposium on High-Performance Computer Architecture (HPCA '08). 191--202.Google Scholar
- Dally, W. J. 1992. Virtual channel flow control. IEEE Trans. Parallel Distrib. Syst., 3, 2, 194--205. Google ScholarDigital Library
- Deb, S., Ganguly, A., Chang, K., Pande, P. P., Belzer, B., and Heo, D. 2010. Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects. In Proceedings of the IEEE International Conference on ASAP. 73--80.Google Scholar
- Deen, M. J. and Marinov, O. 2002. Effect of forward and reverse substrate biasing on low-frequency noise in silicon PMOSFETs. IEEE Trans. Electron. Dev. 49, 3, 409--413.Google ScholarCross Ref
- Draper, J. and Petrini, F. 1997. Routing in bidirectional k-ary n-cube switch the red rover algorithm. In Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications. 1184--93.Google Scholar
- Duato, J., Yalamanchili, S., and Ni, L. 2002. Interconnection Networks—An Engineering Approach. Morgan Kaufmann. Google ScholarDigital Library
- Eiben, A. E. and Smith, J. E. 2003. Introduction to Evolutionary Computing. Springer Berlin. Google ScholarDigital Library
- Floyd, B. A., Hung, C.-M., and O, K. K. 2008. Intra-Chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters. IEEE J. Solid-State Circ. 37, 5, 543--552.Google ScholarCross Ref
- Ganguly, A., Chang, K., Deb, S., Pande, P. P., Belzer, B., and Teuscher, C. 2010. Scalable hybrid wireless network-on-chip architectures for multi-core systems. IEEE Trans. Comput. 99, 1. Google ScholarDigital Library
- Jansen, T. and Wegener, I. 2007. A comparison of simulated annealing with a simple evolutionary algorithm on pseudo-boolean functions of unitation. Theor. Comput. Sci. 386, 73--93 Google ScholarDigital Library
- Joshi, A., Batten, C., Kwon, Y.-J., Beamer, S., Shamim, I., Asanovic, K., and Stojanovic, V. 2009. Silicon-Photonic clos networks for global on-chip communication. In Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS '09). 124--133. Google ScholarDigital Library
- Kathiresan, G. and Toumazou, C. 1999. A low voltage bulk driven down-conversion mixer core. In Proceedings of the IEEE International Symposium on Circuit and Systems. 598--601.Google Scholar
- Kawasaki, K., Akiyama, Y., Komori, K., Uno, M., Takeuchi, H., Itagaki, T., Hino, Y., Kawasaki, Y., Ito, K., and Hajimiri, A. 2010. A millimeter-wave intra-connect solution. IEEE J. Solid-State Circ. 45, 12, 2655--2666.Google ScholarCross Ref
- Kempa, K., Rybczynski, J., Huang, Z., Gregorczyk, K., Vidan, A., Kimball, B., Carlson, J., Benham, G., Wang, Y., Herczynski, A., and Ren, Z. 2007. Carbon nanotubes as optical antennae. Adv. Mater. 19, 421--426.Google ScholarCross Ref
- Kirkpatrick, S., Gelatt, Jr., C. D., and Vecchi, M. P. 1983. Optimization by simulated annealing. Sci. 220, 671--680.Google ScholarCross Ref
- Krishna, T., Kumar, A., Chiang, P., Erez, M., and Peh, L.-S. 2008. NoC with near-ideal express virtual channels using global-line communication. In Proceedings of the IEEE Symposium on High Performance Interconnects (HOTI '08). 11--20. Google ScholarDigital Library
- Kumar, A., Peh, L.-S., and Jha, N. K. 2008a. Token flow control. In Proceedings of the 41st IEEE/ACM International Symposium on Microarchitecture (MICRO '08). 342--353. Google ScholarDigital Library
- Kumar, A., Peh, L.-S., Kundu, P., and Jha, N. K. 2008b. Toward ideal on-chip communication using express virtual channels. IEEE Micro 28, 1, 80--90. Google ScholarDigital Library
- Kurian, G., Miller, J. E., Psota, J., Eastep, J., Liu, J., Michel, J., Kimerling, L. C., and Agarwal, A. 2010. Atac: A 1000-core cache-coherent processor with on-chip optical network. In Proceedings of the Conference on Parallel Architectures and Compilation Techniques (PACT '10). Google ScholarDigital Library
- Lee, S.-B., Tam, S.-W., Pefkianakis, I., Lu, S., Chang, M. F., Guo, C., Reinman, G., Peng, C., Naik, M., Zhang, L., and Cong, J. 2009. A scalable micro wireless interconnect structure for CMPs. In Proceedings of ACM Annual International Conference on Mobile Computing and Networking (MobiCom '09). 20--25. Google ScholarDigital Library
- Lin, J.-J., Wu, H.-T., Su, Y., Gao, L., Sugavanam, A., Brewer, J. E., and O, K. K. 2007. Communication using antennas fabricated in silicon integrated circuits. IEEE J. Solid-State Circ. 42, 8, 1678--1687.Google ScholarCross Ref
- Mehta, J., Bravo, D., and O, K. K. 2002. Switching noise picked up by a planar dipole antenna mounted near integrated circuits. IEEE Trans. Electro-Magnetic Compat. 44, 5, 282--290.Google ScholarCross Ref
- Mensink, E., Schinkel, D., Klumperink, E., Van Tuijl, E., and Nauta, B. 2007. A 0.28pJ/b 2Gb/s/ch transceiver in 90nm CMOS for 10mm on-chip interconnects. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC '07). 414--612.Google Scholar
- Ogras, U. Y. and Marculescu, R. 2006. It's a small world after all: NoC performance optimization via long-range link insertion. IEEE Trans. VLSI Syst. 14, 7, 693-706. Google ScholarDigital Library
- Pande, P. P., Grecu, C., Jones, M., Ivanov, A., and Saleh, R. 2005. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput. 54, 8, 1025--1040. Google ScholarDigital Library
- Pande, P., Clermidy, F., Puschini, D., Mansouri, I., Bogdan, P., Marculescu, R., and Ganguly, A. 2011. Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms? In Proceedings of the Desing, Automation and Test in Europe Conference (DATE'11). 1--6.Google Scholar
- Petermann, T. and De Los Rios, P. 2006. Physical realizability of small-world networks. Phys. Rev. E 73, 026114.Google ScholarCross Ref
- Razavi, B. 2004. A study of injection locking and pulling in oscillators. IEEE J. Solid-State Circ. 39, 9, 1415--1424.Google ScholarCross Ref
- Sedra, A. S. and Smith, K. C. 2004. Microelectronic Circuits, 5th Ed. Oxford University Press. Google ScholarDigital Library
- Seok, E. and Kenneth, K. O. 2005. Design rules for improving predictability of on-chip antenna characteristics in the presence of other metal structures. In Proceedings of the IEEE International Interconnect Technology Conference. 120--122.Google Scholar
- Shacham, A., Bergman, K., and Carloni, L. P. 2008. Photonic networks-on-chip for future generations of chip multiprocessors. IEEE Trans. Comput. 57, 9, 1246--1260. Google ScholarDigital Library
- Shekhar, S., Walling, J. S., and Allstot, D. J. 2006. Bandwidth extension techniques for CMOS amplifiers. IEEE J. Solid-State Circ. 41, 11, 2424--2439.Google ScholarCross Ref
- Sipper, M. 1997. Evolution of Parallel Cellular Machines: The Cellular Programming Approach. Springer Berlin. Google ScholarDigital Library
- Teuscher, C. 2007. Nature-inspired interconnects for self-assembled large-scale network-on-chip designs. Chaos 17, 2, 026106, 2007.Google ScholarCross Ref
- U. E. P. Agency. 2012. Report to congress on server and data center energy efficiency public law 109--431. http://www.energystar.gov/.Google Scholar
- Watts, D. J. and Strogatz, S. H. 1998. Collective dynamics of ‘small-world’ networks. Nature 393, 440--442.Google ScholarCross Ref
- Yao, T., Gordon, M. Q., Tang, K. K. W., Yau, K. H. K., Yang, M.-T., Schvan, P., and Voinigescu, S. P. 2007. Algorithmic design of CMOS LNAs and PAs for 60-GHz radio. IEEE J. Solid-State Circ. 42, 5, 1044--1056.Google ScholarCross Ref
- Yu, X., Sah, S. P., Belzer, B., and Heo, D. 2010. Performance evaluation and receiver front-end design for on-chip millimeter-wave wireless interconnect. In Proceedings of the International Conference on Green Computing (IGCC '10). 555--560. Google ScholarDigital Library
- Zhang, Y. P., Chen, Z. M., and Sun, M. 2007. Propagation mechanisms of radio waves over intra-chip channels with integrated antennas: frequency-domain measurements and time-domain analysis. IEEE Trans. Antennas Propag. 55, 10, 2900--2906.Google ScholarCross Ref
- Zhao, D. and Wang, Y. 2008. SD-MAC: Design and synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip. IEEE Trans. Comput. 57, 9, 1230--1245. Google ScholarDigital Library
Index Terms
- Performance evaluation and design trade-offs for wireless network-on-chip architectures
Recommendations
Complex network-enabled robust wireless network-on-chip architectures
The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data ...
Dual-Level DVFS-Enabled Millimeter-Wave Wireless NoC Architectures
Wireless Network-on-Chip (WiNoC) has emerged as an enabling technology to design low power and high bandwidth massive multicore chips. WiNoCs based on small-world network architecture and designed with incorporating millimeter (mm)-wave on-chip wireless ...
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate ...
Comments