%PDF-1.4
%
1 0 obj
<>stream
application/pdfIEEEIEEE Access;2022;10; ;10.1109/ACCESS.2022.3221742Low-Latency Multi-Kernel Polar DecodersFPGAhardware implementationlow latenypolar codesuccessive cancellationURLLCHossein RezaeiNandana RajathevaMatti Latva-Aho
IEEE Access119460 202210.1109/ACCESS.2022.322174210119474
VoR
endstream
endobj
2 0 obj
<>stream
HWoWTam.-Kr8N::;((jmIs쒔L?+Zggg_ͷx 5IĜ%*xc݊#
4nA8bǃj\?Rd"2sSmz;RYx<,/#M}:rWfGfD~0E1mKq|;O!UGq]e|'߀+(ci'?2iK"rII:jiږQeM4ܷ;qk^+Qy\JYKYt$m#~k۞X-qܔ
+S5m^M=kc6c6;_paϴmكibsh>8MeS3ݖdɃdY XgYg`5&tM;l>'۶ޡm5DYbKo,