Djaafar Chabi
Weisheng Zhao
Jacques-Olivier Klein
Skip Abstract Section
Abstract
Scaling down beyond CMOS transistors requires the combination of new computing paradigms and novel devices. In this context, neuromorphic architecture is developed to achieve robust and ultra-low power computing systems. Memristive nanodevices are often associated with this architecture to implement efficiently synapses for ultra-high density. In this article, we investigate the design of a neuro-inspired logic block (NLB) dedicated to on-chip function learning and propose learning strategy. It is composed of an array of memristive nanodevices as synapses associated to neuronal circuits. Supervised learning methods are proposed for different type of memristive nanodevices and simulations are performed to demonstrate the ability to learn logic functions with memristive nanodevices. Benefiting from a compact implementation of neuron circuits and the optimization of learning process, this architecture requires small number of nanodevices and moderate power consumption.
- Guillaume Agnus, Weisheng Zhao, and Vincent Derycke, et al. 2010. 2-Terminal carbon nanotube programmable devices for adaptive architectures. Adv. Mater. 22, 6, 702--706.Google Scholar
Cross Ref
- Olivier Bichler, Weisheng Zhao, and Fabien Alibart, et al. 2010. Functional model of a nanoparticle organic memory transistor for use as a spiking synapse. IEEE Trans. Electron. Dev. 57, 11, 3115--3122.Google ScholarCross Ref
- Olivier Bichler, Weisheng Zhao, and Fabien Alibart, et al. 2013. Pavlov's dog associative learning demonstrated on synaptic-like organic transistors. MIT press journals. Neural Computat. 25, 549--566. Google ScholarDigital Library
- Julien Borghetti, Zhiyong Li, and Joseph Straznicky, et al. 2009. A hybrid nanomemristor/transistor logic circuit capable of self-programming. Proc. Nat. Acad. Sci. USA, 106, 6, 1699--1703.Google ScholarCross Ref
- Julien Borghetti, Gregory S. Snider, and Philip J. Kuekes, et al. 2010. Memristive switches enable stateful logic operations via material implication. Nature. 464, 873--876.Google ScholarCross Ref
- Djaafar Chabi and Jacques-Olivier Klein. 2010. Height fault tolerance in neural crossbar. In Proceedings of the 5th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 23--25.Google ScholarCross Ref
- Djaafar Chabi, Weisheng Zhao, Damien Queriloz, and Jacques-Olivier Klein. 2011. Robust neural logic block (NLB) based on memristor crossbar array. In Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 137--143. Google ScholarDigital Library
- Djaafar Chabi, Weisheng Zhao, Damien Queriloz, and Jacques-Olivier Klein. 2014. Robust learning approach for neuro-inspired nanoscale crossbar architecture. ACM J. Emerg. Tech. Comput. Syst. 10, 1, 5. Google ScholarDigital Library
- David Choi, Kyu Choi, and John D. Villasenor. 2008. New non-volatile memory structures for FPGA architectures. IEEE Trans. (VLSI) Syst. 16, 7. Google ScholarDigital Library
- Hyejung Choi, Heesoo Jung, and Joonmyoung Lee, et al. 2009. An electrically modifiable synapse array of resistive switching memory. Nanotechnology. 20, 34, 345201.Google ScholarCross Ref
- Yoon-Hwa Choi, Myeong-Hyeon Lee, and Young Kwan Kim. 2004. A two-level redundancy scheme for enhancing scalability of molecular-based crossbar memories. In Proceedings of 4th IEEE Conference on Nanotechnology, 505--508.Google Scholar
- Stephen Y. Chou, Peter R. Krauss, and Preston J. Renstrom. 1995. Imprint of sub-25 nm vias and trenches in polymers. Appl. Phys. Lett. 67, 21, 3114.Google ScholarCross Ref
- Leon O. Chua and Sung Mo Kang. 1976. Memristive devices and systems. Proc. IEEE 64, 209--223.Google ScholarCross Ref
- André DeHon and Konstantin K. Likharev. 2005. Hybrid CMOS/nanoelectronic digital circuits: Devices, architectures, and design automation. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 375--382. Google ScholarDigital Library
- Dimitrios Simos, Ioannis Papaefstathiou, and Manolis Katevenis. 2008. Building an FoC using large, buffered crossbar cores. IEEE Design Test Comput. 5, 538--548. Google ScholarDigital Library
- Karim Gacem, Jean-Marie Retrouvey, Djaafar Chabi, et al. 2013. Neuromorphic function learning with carbon nanotube based synapses. Nanotechnology 24, 384013.Google ScholarCross Ref
- Pierre-Emmanuel Gaillardon, D. Sachetto, G. B. Beneventi, and M. H. Ben Jamma, et al. 2013. Design and architectural assessment of 3-D resistive memory technologies in FPGAs. IEEE Trans. Nanotechnol. 12, 1. Google ScholarDigital Library
- Chakku Gopalan, Yi Ma, and T. Gallo, et al. 2011. Demonstration of conductive bridging random access memory (CBRAM) in logic CMOS process. Solid-State Electron. 58, 1, 54--61.Google ScholarCross Ref
- Tsuyoshi Hasegawa, Takeo Ohno1, and Kazuya Terabe1, et al. 2010. Learning abilities achieved by a single solid state atomic switch. Adv. Mater. 22, 16, 1831--1834.Google ScholarCross Ref
- Michel He, J.-O. Klein and Eric Belhaire. 2008. Design and electrical simulation of on-chip neural learning based on nanocomponents. Electron. Lett. 44, 9, 575--576.Google ScholarCross Ref
- Yu Huang, Xiangfeng Duan, and Yi Cui, et al. 2001. Logic gates and computation from assembled nanowire building blocks. Science. 294, 5545, 1313--1317.Google Scholar
- Sung Hyun Jo, Kuk-Hwan Kim, and Wei Lu. 2009. Programmable resistance switching in nanoscale two-terminal devices. Nano Lett. 9, 1, 496--500.Google ScholarCross Ref
- Sung Hyun Jo, Ting Chang, and Idongesit Ebong, et al. 2010. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett. 10, 4, 1297--1301.Google ScholarCross Ref
- Philip J. Kuekes, Warren Robinett, Gadiel Seroussi, and R. Stanley Williams. 2005. Defect-tolerant interconnect to nanoelectronic circuits: Internally redundant demultiplexers based on error-correcting codes. Nanotechnology 16, 869--882.Google ScholarCross Ref
- Qianxi Lai, Lei Zhang, Zhiyong Li, et al. 2010. Ionic/electronic hybrid materials integrated in a synaptic transistor with signal processing and learning functions. Adv. Mater. 22, 22, 2448--2453.Google ScholarCross Ref
- Jung Hoon Lee and Konstantin K. Likharev. 2007. Defect-tolerant nanoelectronic pattern classifiers. Int. J. Circuit Theory Appl. 35, 3, 239--264. Google ScholarDigital Library
- Yubao Li, Alexander Sinitskii, and James M. Tour. 2008. Electronic two-terminal bistable graphitic memories. Nat Mater. 7, 12, 966--971.Google ScholarCross Ref
- Jiale Liang and H.-SP Wong. 2010. Cross-point memory array without cell selectors—device characteristics and data storage pattern dependencies. IEEE Trans. Electron Devices 57, 2531--2538.Google ScholarCross Ref
- Si-Yu Liao, Montassar Najari, Cristell Maneux, et al. 2011. Design of neuro-inspired learning circuit using OG-CNTFET modelling and technology, IEEE Trans. Circ. Syst. Regul. Pap. 58, 2172--2181.Google ScholarCross Ref
- Eike Linn, Roland Rosezin, Carsten Kügeler, et al. 2010. Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 9, 5, 403--406.Google ScholarCross Ref
- Bo Liu, Zhitang Song, Songlin Feng, and Bomy Chen. 2005. Characteristics of chalcogenide nonvolatile memory nano-cell-element based on Sb2Te3 material. Microelectron. Eng. 82, 2, 168--174. Google ScholarDigital Library
- Wei Lu and Charles M. Lieber. 2007. Nanoelectronics from the bottom up. Nat Mater. 6, 11, 841--850.Google ScholarCross Ref
- Konstantin Nikolic, Akram Sadek, and Michael Forshaw. 2002. Fault-tolerance technique for nanocomputer. Nanotechnol. 13, 280--346.Google ScholarCross Ref
- Seonyeong Park, Youngjae Kim, and Bhuvan Urgaonkar, et al. 2011. A comprehensive study of energy efficiency and performance of flash-based SSD. J. Syst. Archit. 57, 354--365. Google ScholarDigital Library
- Yuriy V. Pershin and Massimiliano Di Ventra. 2010. Experimental demonstration of associative memory with memristive neural networks. Neural Netw. 23, 7, 881--886. Google ScholarDigital Library
- Pujol Hubert, Jacques-Olivier Klein, Eric Belhaire, and Patrick Garda. 1994. RA: An analog neurocomputer for the synchronous Boltzmann machine. In Proceedings of the 4th International Conference on Microelectronics for Neural Networks and Fuzzy Systems. 449--455.Google Scholar
- Damien Querlioz, Olivier Bichler, and Christian Gamrat. 2011a. A memristor-based spiking neural network immune to device variations. In Proceedings of the International Joint Conference on Neural Networks (IJCNN), 1775--1781.Google ScholarCross Ref
- Damien Querlioz, Philippe Dollfus, Olivier Bichler, and Christian Gamrat. 2011b. Learning with memristive devices: How should we model their behavior? In Proceedings of IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). 150--156. Google ScholarDigital Library
- José Antonio Pérez-Carrasco, C. Zamarreño-Ramos, T. Serrano-Gotarredina, and B. Linares-Barranco. 2010. On neuromorphic spiking architectures for asynchronous STDP memristive systems. In Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 1659--1662.Google Scholar
- Kyungah Seo, Insung Kim, and Seungjae Jung, et al. 2011. Analog memory and spike-timing-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device. Nanotechnology 22, 25, 254023.Google ScholarCross Ref
- Gregory S. Snider. 2007. Self-organized computation with unreliable, memristive nanodevices. Nanotechnology 18, 36, 365202.Google ScholarCross Ref
- Gregory S. Snider. 2008. Spike-timing-dependent learning in memristive nanodevices. In Proceedings of IEEE International Symposium on Nanoscale Architectures (NANOARCH), 85--92. Google ScholarDigital Library
- Gregory S. Snider. 2011. Instar and outstar learning with memristive nanodevices. Nanotechnology 22, 1, 015201.Google ScholarCross Ref
- Dmitri B. Strukov and Konstantin K. Likharev. 2005. CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices RID B-2689-2009. Nanotechnology 16, 6, 888--900.Google ScholarCross Ref
- Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart, and R. Stanley Williams. 2008. The missing memristor found. Nature. 453, 80--83.Google ScholarCross Ref
- Dmitri B. Strukov and R. Stanley Williams. 2009. Four-dimensional address topology for circuits with stacked multilayer crossbar arrays. Proc. Nat. Acad. Sci. USA 106, 48, 20155--20158.Google ScholarCross Ref
- D. Tank and John J. Hopfield. 1986. Simple 'neural' optimization networks: An A/D converter, signal decision circuit, and a linear programming circuit. IEEE Trans. Circuits Systems. 33, 5, 533.Google ScholarCross Ref
- James M. Tour, Long Cheng, and David P. Nackashi, et al. 2003. NanoCell electronic memories. J. Amer. Chem. Soc. 125, 43, 13279--13283.Google ScholarCross Ref
- Massimiliano Versace and Ben Chandler. 2010. The brain of a new machine. IEEE Spectrum 47, 12, 30--37. Google ScholarDigital Library
- Pascal O. Vontobel, Warren Robinett, Philip J. Kuekes, and Duncan R. Stewart, et al. 2009. Writing to and reading from a nano-scale crossbar memory based on memristors. Nanotechnology 20, 42, 425204.Google ScholarCross Ref
- Frank Zhigang Wang, Helian Na, and Sining Wu, et al. 2010. Delayed switching in memristors and memristive systems. IEEE Electron. Devi. Lett. 31, 755--757.Google ScholarCross Ref
- Zhaohao Wang, Weisheng Zhao, and Wang Kang, et al. 2014. Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture. In Proceedings of the International Joint Conference on Neural Networks (IJCNN), 29--34.Google ScholarCross Ref
- Rainer Waser. 2009. Resistive non-volatile memory devices. Microelectron. Eng. 86, 7--9, 1925--1928. Google ScholarDigital Library
- Bernard Widrow and Marcian E. Hoff. 1960. Adaptive switching circuits. IRE WESCON Convention Record, 96--104.Google Scholar
- Qiangfei Xia, Warren Robinett, and Michael W. Cumbie, et al. 2009. Memristor-CMOS hybrid integrated circuits for reconfigurable logic. Nano Lett. 9, 3640--5.Google ScholarCross Ref
- J. Joshua Yang, Julien Borghetti, David Murphy, Duncan R. Stewart, and R. Stanley Williams. 2009. A family of electronically reconfiguiable nanodevices. Adv. Mater. 21, 3754--3758.Google ScholarCross Ref
- Shimeng Yu, Yi Wu, and H.-S. Philip Wong. 2011. Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory. Appl. Phys. Lett. 98, 10, p. 103514.Google ScholarCross Ref
- Weisheng Zhao, Guillaume Agnus, and Vincent Derycke, et al. 2010. Nanotube devices based crossbar architecture: Toward neuromorphic computing, Nanotechnology 21, 175202.Google ScholarCross Ref
- Weisheng Zhao, Celso Accoto, and Jacques-Olivier Klein, et al. 2012. Cross-point architecture for spin transfer torque magnetic random access memory. IEEE Trans. Nanotechnology 11, 907--917. Google ScholarDigital Library
Index Terms
- On-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices
Recommendations
Robust learning approach for neuro-inspired nanoscale crossbar architecture
Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011Scaling beyond CMOS require a new combination of computing paradigm and new devices. In this context, memristor are often considered as best candidate to implement efficiently synapses in hardware neural networks. In this article, we analyze the impact ...
Spike-timing-dependent learning in memristive nanodevices
NANOARCH '08: Proceedings of the 2008 IEEE International Symposium on Nanoscale ArchitecturesThe neuromorphic paradigm is attractive for nanoscale computation because of its massive parallelism, potential scalability, and inherent defect-, fault-, and failure-tolerance. We show how to implement timing-based learning laws, such as spike-timing-...
On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron
NANOARCH '14: Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale ArchitecturesThe memristor-based neural learning network is considered as one of the candidates for future computing systems thanks to its low power, high density and defect-tolerance. However, its application is still hindered by the limitations of huge neuron ...
Comments