Hysteresis suppression in self-assembled single-wall nanotube field effect transistors

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Abstract

We present a technique for hysteresis suppression in single-wall nanotube field effect transistors (SWNT-FETs) using chemical functionalization. We selectively modify the electrode surfaces and the device channel area with self-assembled monolayers (SAMs) of octanethiol and aminopropyltriethoxysilane (APTES), respectively. These can efficiently prevent surface adsorption of water molecules. We show that hysteresis is suppressed, with a 15 times decrease in hysteresis gap compared to the conventional SWNT-FETs on bare SiO2/Si.

Introduction

Single-wall carbon nanotube field-effect transistors (SWNT-FETs) are outstanding candidates for future nanoelectronics. To date, remarkable progress has been made in improving the ON/OFF ratio, carrier mobility and sub-threshold slope (S) by different approaches. These include (1) reduction of the gate oxide thickness [1]; (2) adoption of high-K gate dielectrics [2], [3], [4]; (3) use of electrolyte as gate dielectric [5], [6]; (4) reduction of contact resistance using appropriate contact metals [7] and post-process treatments [8].

Hysteresis is an important performance factor for SWNT-FETs. During transfer characteristics (TCs) measurements, many SWNT-FETs exhibit hysteresis between the forward and reverse gate voltage sweeps, resulting in an apparent shift in the threshold voltage, sub-threshold slope and the current [9], [10], [11], [12]. This is usually explained by charge injection from SWNTs into the oxide layer at large gate bias where the charges are trapped until the polarity is reversed [11], [12], [13], [14]. Adsorbed molecules (e.g. water molecules) may also increase this effect by providing additional trap sites [10]. It has been reported that SWNT-FETs fabricated on SiO2/Si substrates exhibit hysteresis in current versus gate–voltage characteristics (Si as back-gate) [12], [13], [14]. This was attributed either to charge traps in bulk SiO2 [12], or to oxygen-related defect traps sites near SWNTs [13], or to traps at the SiO2/Si interface [14]. Recently, the dependence of the hysteresis on the chemical environment was also investigated [10]. Ref. [10] attributes hysteresis to charge trapping from water molecules around the SWNTs, including SiO2 surface-bound water molecules in close proximity to the SWNTs [10].

Hysteresis can be used for the development of memory devices [11], [12], [13], [14], [15]. However, SWNT-FET-based electronic applications (e.g. sensors [16], [17], [18], logic circuit [2], [19], [20]) require stable transport properties. Therefore, it is necessary to suppress hysteresis for such devices. Ref. [10] reported a technique to protect nanotube channels from ambient humidity by encasing the FET in a polymer. But such approach impedes further circuit integration of SWNT-FETs because the encased device is impossible to connect. Also, for applications such as sensing, this technique is unsuitable since the encased FET cannot be functionalized with or exposed to chemicals and biomolecules. In this work, we demonstrate a new technique for hysteresis suppression by chemically functionalizing the surfaces where the SWNTs are deposited. This decreases the surface trap sites and prevents the adsorption of water molecules. In contrast to Ref. [10], our proposed method allows further integration of SWNT-FETs and their use in sensing.

Section snippets

Experimental

We consider two sets of SWNT-FETs: one with SWNTs directly deposited on the bare SiO2/Si wafer (FET on SiO2) and the other with SWNTs deposited on the SiO2/Si coated with organic self-assembled monolayers (FET on SAM).

For FET on SiO2, we grow SWNTs on SiO2/Si using horse-spleen ferritin (Sigma-Aldrich) as the source of Fe catalyst [21]. Growth takes place in a 2-in diameter quartz tube furnace by heating up in an argon flow of 1000 sccm–900 °C. The growth is initiated by introducing methane at 500

Results and discussion

Fig. 1 plots the schematic structure of the FET on SAM with back gate used in this study. The SWNTs lie on the APTES modified Si/SiO2 surface, contacting the two electrodes covered with octanethiol monolayer (source and drain). Previous studies showed that SWNTs tend to deposit in areas covered with polar chemicals when the wafer is dipped in a SWNT solution [23], [24]. Since the area between our electrodes is functionalized with a polar APTES SAM, we find that the SWNTs are selectively

Conclusions

We developed a technique to suppress hysteresis in SWNT-FET via a selective surface functionalization with SAMs. These hydrophobic SAMs can efficiently prevent surface adsorption of water molecules in SWNT-FETs. Compared to SWNT-FETs on bare SiO2/Si surface, the hysteresis in SWNT-FETs on SAM is suppressed efficiently and the hysteresis gap in our experiments is reduced by a factor of about 15. These FETs on SAM deliver stable electric properties, and they are suited to be used for nanoscale

Acknowledgments

This work was supported by the Ministry of Information and Communication, Republic of Korea, under Project no. A1100-0602-0101. ACF acknowledges funding from the Royal Society and the Leverhulme Trust.

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