Defect evolution and dopant activation in laser annealed Si and Ge

Abstract

Defect evolution and dopant activation are intimately related to the use of ion implantation and annealing, traditionally used to dope semiconductors during device fabrication. Ultra-fast laser thermal annealing (LTA) is one of the most promising solutions for the achievement of abrupt and highly doped junctions. In this paper, we report some recent investigations focused on this annealing method, with particular emphasis on the investigation of the formation and evolution of implant/anneal induced defects and their impact on dopant activation. In the case of laser annealed Silicon, we show that laser anneal favours the formation of “unconventional” (001) loops that, following non-melt anneals, act as carrier scattering centres, leading to carrier mobility degradation. In contrast, in the case of melt anneals, the molten region itself is of excellent crystalline quality, defect-free and with very high activation rates. As for laser annealed Germanium, we studied in detail the amorphous to crystalline Ge phase transition as a function of the increasing LTA energy density and we found that using LTA, very high carrier concentrations (above 10²⁰ cm⁻³) were achieved in As doped regions, which are unachievable with conventional rapid thermal annealing (RTA) processes.

Introduction

During the last decade, the miniaturisation of planar “bulk Si” MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) through the “traditional” geometrical scaling approach has become extremely difficult, due to the uncontrolled increase of short channel effects (and consequently of power consumption) [1]. Several solutions were developed to mitigate such effects (high-k/metal gate, strain engineering, ultra-thin Silicon-on-Insulator (SOI) substrates, 3D nano-fabrication…), which could be eventually combined into one technology process. As a consequence, a considerable diversification of the possible device architectures for future nodes occurred: today, the most advanced MOS device architectures range from (still) planar Fully-Depleted (FD)-SOI transistors, to 3D multigate FinFETs or gate-all-around nanowire (NW)-FETs (cf. Fig. 1). Doping requirements of source/drain (S/D) regions may therefore differ depending on the specific device architecture.

In modern FD-SOI technology, the doping of the raised source/drain (RSD, or High-Doped Drain, HDD) is achieved in situ during the growth of the RSD layer, while the use of ion implantation for S/D extension doping (or Low-Doped Drain, LDD) is a major technological challenge, considering the need to achieve a controlled lateral diffusion/abruptness, with limited damage in a nanometric layer [2], [3]. Additionally, novel approaches based on ion implantation have been proposed for the control of the “extrinsic” resistance components of the S/D module (silicide, Schottky barrier height and contact metal). These include the use of ultra-low energy implants to increase the dopant concentration at the semiconductor/silicide interface [4] or the segregation of implanted dopants to lower the Schottky Barrier height [5], [6].

Additional critical issues need to be considered for 3D FinFETs. One is the reduction of damage formation during annealing, which is impossible to avoid when amorphisation occurs during the implant [7]. To this respect, high-temperature “hot” implants [8] have been proposed to reduce damage accumulation during the implant. The second is conformal doping [9]. In fact, conventional beamline implants can only be performed using low-angle tilted beams due to fin/photo resist shadowing [10]. Plasma immersion ion implantation [11], [12] or other plasma-related doping methods [13], [14] are the most promising candidates to improve conformality in fin doping [15]. Finally, it is important to note that dopant conformality is a critical issue also for CMOS imagers, where deep trench isolation between neighbour MOS cells is achieved by forming shallow doped junctions at the surfaces of the trenches [16].

Nanowire-based field effect transistors (NW-FETs) are among the most promising solutions to overcome the limits of today’s electronic devices, especially for their ability to implement gate-all-around architectures [17]. NW doping can be achieved in-situ during growth [18] or ex-situ following several methods (diffusion [19], molecular doping [20], [21], ion implantation [22]), However, the efficiency of each one of these methods critically depends on several parameters and physical phenomena [23], [24], including NW material, size or surface passivation. As a consequence, while alternative doping-free S/D fabrication schemes based on the implementation of “Schottky contacts” are being developed [25], reliable and systematic studies of ion implantation-doped NWs are still lacking. Indeed, opposite results show either a reduced amount of structural disorder in implanted Si-NWs compared to bulk Si [26] or an “unrecoverable” amorphisation damage during annealing [7].

A crucial step in the fabrication of S/D doped region is the thermal anneal required for damage recovery and dopant activation. In parallel to the evolution of device architectures, thermal annealing has also evolved during the last decade towards shorter cycles combined with higher temperatures, so to combine controllable diffusion with high activation [27]. Currently used “spike” Rapid Thermal Anneals (RTA), with ramping rates in the order of 250 °C/s, are expected to be replaced with even faster methods operating in the millisecond or nanosecond scale. In particular, the recent advances in nanosecond laser annealing have opened the way to solve a wide spectrum of difficult challenges in semiconductor technology, well beyond the S/D fabrication issues. Indeed, thanks to the low thermal budget of a laser pulse (with duration in the nanosecond regime), laser annealing is very attractive not only for the achievement of abrupt junctions [28], [29], [30], but more generally for all semiconductor technologies in which dopants need to be activated while preserving the integrity of the surrounding areas, as in the case of thin film displays [31], high‐frequency bipolar silicon‐on‐glass processes [32], CMOS backside imagers [33], [34] or 3D integration schemes [35], [36], for which localised laser annealing is a promising alternative to low temperature (<600 °C) Solid Phase Epitaxy processes [37].

However, several issues still need to be investigated to achieve a thorough understanding of the underlying physics, improve the predictive modelling of dopant redistribution during laser process and ultimately optimise the process conditions. They range from the non‐uniform absorption of the radiation up to the kinetically limited segregation of dopants and intrinsic point defects during liquid‐phase epitaxy. A particularly important challenge is the role of residual damage on the activation of dopants, its evolution during laser processing and its stability during post‐implantation annealing at lower temperatures.

In this paper, we will focus on damage related issues, by presenting some recent investigations focused on damage evolution and its impact on dopant distribution and electrical activation during nanosecond laser thermal annealing of ion implanted group IV semiconductors. Section 2 will concern Si, while recent results on Germanium will be reported in Section 3.