Moore’s crystal ball: Device physics and technology past the 15 nm generation
Graphical abstract
Introduction
For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. An excellent example is provided by SRAM scaling over the last five generations, where steady adherence to Moore’s Law has delivered 2X bitcell area scaling each generation (see Fig. 1).
As we look forward to the 15 nm node and beyond, there are a number of critical challenges to be addressed. These challenges include reducing the effective gate length (Leff), reducing the gate pitch, and targeting the threshold voltage (VT).
Reducing Leff is a critical challenge for advanced technology generations. Increased off-state current (Ioff) from degraded drain-induced barrier lowering (DIBL) and subthreshold slope (SS) caused by poorer short channel effects (SCE) represents a significant limitation for Leff shorter than approximately 15 nm. Decreasing the gate oxide thickness (Tox) to provide better channel control comes with a penalty of increased gate leakage current (Igate) and increased channel doping (to increase threshold voltage, VT) to maintain Ioff. Increased channel doping decreases mobility (degrading performance due to impurity scattering), as well as increasing random dopant fluctuations (RDF). Increasing RDF increases variation in VT with subsequent impact to the minimum operating voltage (Vmin).
Reducing gate pitch is also a critical challenge for advanced technology generations. Decreasing gate pitch decreases the stress enhancement for both NMOS (stress induced by overlayer films) and PMOS (stress induced by embedded-SiGe, e-SiGe) thus decreasing mobility and drive. Decreasing gate pitch increases the parasitic capacitance contribution for both contact-to-gate and epi-to-gate thus increasing overall gate capacitance (Cgs). Finally, decreasing the source/drain opening size increases the source drain resistance (Rsd) thus decreasing drive current.
Targeting VT is a critical challenge for advanced technology generations, particularly for the low power system-on-chip (SOC) processes. The critical conflict is between the need for higher VT (to produce lower Ioff and reduce stand-by power) and the need for lower VT (to produce lower Vmin and reduce active power).
Section snippets
Improving electrostatic confinement
Maintaining the scaling roadmap will require continual improvement in short channel properties. A variety of device architectures which improve electrostatic confinement (and thus short channel control) are being investigated for advanced technology nodes. These architectures can be broadly categorized by the method of electrostatic confinement. There are architectures which provide additional electrostatic confinement with a planar architecture (ultra-thin body (UTB), fully-depleted SOI
Mobility enhancements
Maintaining the scaling roadmap will require continual improvement in channel mobility. Short term approaches include reorienting the surface or channel of the device, and implementing improved strain techniques. Long term solutions may include more exotic channel materials (Ge, III–V, etc.).
Resistance and next generation transistors
Improving the traditional resistive elements, such as the accumulation (Racc), spreading, silicide and contact resistances, will become more challenging at the reduced dimensions of advanced technologies. Furthermore, resistance elements previously neglected (including interface and epi resistance) are becoming significant issues. Moreover, the various non-planar architectures will introduce new resistance components associated with small dimension fins and wires.
All these resistive components
Capacitance and next generation transistors
Improving the traditional capacitance elements, such as under-lap capacitance (Cxud), channel capacitance, junction capacitances (both gated edge and area) and the inner and outer fringe capacitance; will become more challenging at the reduced dimensions of advanced technologies. Furthermore, in recent generations, gate and contact critical dimensions have been scaling slower than contacted gate pitch. This means that parasitic fringe capacitances (for example, contact-to-gate and epi-to-gate)
Conclusions and summary
While significant transistor challenges (SCE, resistance, capacitance, mobility, etc.) exist for technologies past 15 nm, numerous solutions are being explored to drive Moore’s Law forward. Advanced junction engineering will play a critical role in the transistor roadmap past 15 nm.
References (105)
- T.J.K. Liu, L. Chang, Into the Nano Era, vol. 106, Springer, 2009 (chapter...
- et al.
IEEE Trans. Electron. Devices
(1983) IEEE Electron. Device Lett.
(1985)IEEE Electron. Device Lett.
(1986)IEEE Electron. Device Lett.
(1988)- M. Chan et al., in: IEEE International SOI Conference, 1993, pp....
IEEE Electron. Device Lett.
(2000)- B. Doris et al., in: 2005 Symp. on VLSI Tech., June 2005, pp....
- C. Gallon, in: IEEE International SOI Conference, 2006, pp....
- F. Andrieu et al., in: 2006 Symp. on VLSI Tech., June 2006, pp....
IEEE Trans. Electron. Devices
IEEE Electron. Device Lett.
IEEE Electron. Device Lett.
IEEE Trans. Electron. Devices
IEEE Electron. Device Lett.
IEEE Electron. Device Lett.
IEEE Electron. Device Lett.
IEEE Trans. Electron Devices
IEEE Electron. Device Lett.
Cited by (46)
Thin Film Deposition for Front End of Line: The Effect of the Semiconductor Scaling, Strain Engineering and Pattern Effects
2018, Handbook of Thin Film Deposition: Fourth EditionCharacteristics of low-κ SiOC films deposited via atomic layer deposition
2018, Thin Solid FilmsCitation Excerpt :Among these films, SiOC is considered to be the most promising. SiOC possesses the lowest dielectric constant among the candidates and also exhibits good electrical stability, thermal stability, and etch selectivity against SiO2 [4,5,6,7]. Carbon content within the SiOC films is responsible for lowering the dielectric constant by two factors: porosity and polarization.
Analytical modeling and numerical simulation of novel double-gate InGaAs vertical nanowire transistor device for threshold voltage tuning and improved performance
2016, Engineering Science and Technology, an International JournalCitation Excerpt :At or beyond this node, vertical device architecture can bring in new perspectives with regards to increasing device density and improving performance simultaneously. As the semiconductor industry has to grow more number of devices in a limited area, Vertical Nanowire transistors can be the future candidates in building up low power devices and circuits [2]. The Vertical Nanowire FET is a promising device because of its better short channel effect control by improved gate controllability and the high performance ballistic transport [3].
Atomically-thin layered films for device applications based upon 2D TMDC materials
2016, Thin Solid FilmsBand diagram for low-k/Cu interconnects: The starting point for understanding back-end-of-line (BEOL) electrical reliability
2016, Microelectronics ReliabilityCitation Excerpt :As the nano-electronics industry continues dimensional scaling into the single digit nanometer regime in a relentless pursuit to maintain Moore's Law [1–3], back-end-of-line (BEOL) interconnect performance and reliability are becoming increasingly important [4–7].