Abstract
In this paper, a comprehensive analysis of the electrostatics of top-electrode vertically aligned quantized Si nanowire metal–insulator–semiconductor (MIS) structure is performed by formulating a self-consistent analytical model with simultaneous solution of Schrodinger and Poisson equations. The impact of high-k dielectrics on the electrostatic control of such quantized nanowire MIS devices is studied in detail. The electrostatic control is observed to degrade significantly for such high-k insulators with identical equivalent oxide thickness (EOT) due to the nonlinear dependence between dielectric constant and EOT in quantized nanowire MIS devices. The distribution of 3D confined charges along the nanowire is primarily governed by the generated quantum states which are a nonlinear function of the applied voltage. The electrostatic integrity of such device is investigated in terms of simultaneously maintaining the electrostatic control and reduction in carrier tunneling probability. In this context, the impact of several controlling parameters such as applied voltage, barrier height of the insulator/semiconductor junction, carrier effective mass of the insulator and nanowire diameter on tunneling probability is examined. The results suggest insulator effective mass (high-m*) to be the more significant parameter for maintaining electrostatic integrity than its dielectric constant (high-k) in quantized nanowire top-electrode MIS devices.
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Acknowledgements
Mr. Subhrajit Sikdar thanks the University Grant Commission (UGC), Government of India, for funding the fellowship through University of Calcutta. The authors also thank the Center of Excellence (COE) for the Systems Biology and Biomedical Engineering, and Center for Research in Nanoscience and Nanotechnology (CRNN), University of Calcutta, for providing the necessary infrastructural support.
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Sikdar, S., Chowdhury, B.N. & Chattopadhyay, S. Understanding the electrostatics of top-electrode vertical quantized Si nanowire metal–insulator–semiconductor (MIS) structures for future nanoelectronic applications. J Comput Electron 18, 465–472 (2019). https://doi.org/10.1007/s10825-019-01321-7
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DOI: https://doi.org/10.1007/s10825-019-01321-7