Abstract
The steady miniaturization of the metal-oxide-semiconductor field-effect transistor (MOSFET) with each new generation of complementary-MOS (CMOS) technology has yielded continual improvements in integrated-circuit performance and cost per function for more than 40 years. Until recently, transistor scaling generally followed simple rules [1] with slight modification (Table 8.1) [2, 3] to provide for improvements in circuit speed and density with reduction in power consumption per function, while maintaining reliability and electrostatic integrity (gate voltage control of the source-to-channel potential barrier) of the device itself. As a result, MOSFET scaling was able to progress at an exponential rate [4], yielding commensurate improvements in integration, cost, and performance, with revolutionary impact to usher in the Information Age.
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Liu, T.J.K., Chang, L. (2009). Transistor Scaling to the Limit. In: Huff, H.R. (eds) Into the Nano Era. Springer Series in Materials Science, vol 106. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74559-4_8
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